Constraint based retiming of synchronous circuits

Details Constraint based retiming of synchronous circuits Constraint based retiming of synchronous circuits

2011-05-17

2011-05-17

Rossoshek, Helen (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S101000, C716S103000, C716S106000, C716S108000, C716S109000, C716S110000, C716S113000, C716S117000

Reexamination Certificate

active

07945880

ABSTRACT:
In one embodiment of the invention, a method of retiming a circuit is disclosed. The method includes computing an upper bound and a lower bound for a clock period of a clock signal to clock a circuit in response to a netlist of the circuit; selecting a potential clock period for the clock signal to clock registers of the circuit in response to the computed upper bound and the computed lower bound for the clock period; computing an upper bound and a lower bound of a retiming value for each node of the circuit to determine if a retiming of the circuit is achievable with the potential clock period; and computing the retiming value for each node of the circuit to minimize circuit area in response to the computed upper bound and the computed lower bound of the retiming value for each node.

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