Dynamic critical path detector for digital logic circuit paths

Details Dynamic critical path detector for digital logic circuit paths Dynamic critical path detector for digital logic circuit paths

2011-05-10

2011-05-10

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S108000, C716S111000, C716S112000, C716S113000, C716S136000

Reexamination Certificate

active

07941772

ABSTRACT:
Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path.

REFERENCES:
patent: 6415402 (2002-07-01), Bishop et al.
patent: 2006/0263913 (2006-11-01), Marshall
patent: 2007/0164787 (2007-07-01), Grochowski et al.
patent: 2009/0115468 (2009-05-01), Berthold et al.
patent: 99/17186 (1999-04-01), None

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