CMOS device on ultrathin SOI with a deposited raised...
CMOS device structure with reduced risk of salicide bridging and
CMOS device using additional implant regions to enhance ESD...
CMOS device with deep current path for ESD protection
CMOS device with dual polycide gates and method of...
CMOS device with improved performance and method of...
CMOS device with improved wiring density
CMOS device with stressed sidewall spacers
CMOS device with trench structure
CMOS device with zero soft error rate
CMOS devices adapted to prevent latchup and methods of...
CMOS devices hardened against total dose radiation effects
CMOS devices having minimized drain contact area
CMOS devices with graded silicide regions
CMOS diodes with dual gate conductors, and methods for...
CMOS ESD protection structure
CMOS FET with P-well with P- type halo under drain and...
CMOS gate stack
CMOS gates formed by integrating metals having different...
CMOS image device with polysilicon contact studs