CMOS device with trench structure

Details CMOS device with trench structure CMOS device with trench structure

2002-06-11

2003-11-04

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S374000, C257S376000

Reexamination Certificate

active

06642583

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of Japanese Application No. JP 2001-175579, filed Jun. 11, 2001 in the Japanese Patent Office, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device used as a high voltage driver to drive and control a power supply or other equipment.
2. Description of the Related Art
An integrated circuit used as a high voltage driver to drive and control a power supply generally includes a structure to isolate a high voltage portion from a low voltage portion.
Commonly used types of isolating structures include junction a isolation structure using a pn junction and a dielectric isolation structure using a dielectric, such as SiO
2
. In the junction isolation, a p-type substrate, for example a wafer, may be used having a low concentration n-type epitaxial layer formed on a surface of the wafer. A deep p-type diffusion region is formed in the epitaxial layer to form an n-type island that is three dimensionally divided by a pn junction. A driver circuit including a CMOS for example, is fabricated in the n-type island. A high breakdown voltage is achieved by applying reverse voltage between the n-type island and the p-type substrate to electrically isolate the n-type island using a junction capacitance.
In the dielectric isolation, silicon n-regions are formed that are electrically isolated each other by SiO
2
selectively formed in a silicon substrate. An electric circuit is formed in each silicon n-region, where the electric circuit operating at a different base potential from a base potential of the other silicon n-regions. Thus, a high breakdown voltage is achieved in the dielectric isolation.
Japanese Unexamined Patent Application Publication No. H9-55498 discloses a method for junction isolation, in which only a planar junction performs isolation using a conventional silicon wafer, without using an epitaxial wafer that is commonly used in junction isolation. This isolation structure can be regarded as a kind of self-isolation structure. Japanese Unexamined Patent Application Publication No. 2000-58673 discloses a structure combining junction isolation and trench isolation and a trench isolation structure that forms an insulating layer along the surface of a trench.
The junction isolation structure needs relaxation of an electric field concentration at the pn junction appearing on the substrate surface. A commonly used method for the relaxation is a RESURF (reduced surface electric field) structure.
When a reverse bias potential is applied between an isolated n-type region and a p-type substrate, a parallel plane junction corresponding to a bottom of the planar junction develops a depletion layer parallel to the substrate surface. However, an end portion of the n-type region hardly extends the depletion layer and tends to generate the electric field concentration. The RESURF structure sets the impurity concentration in the end portion of the n-type region to a low value so as to facilitate expanding the depletion layer in this portion.
Another structure called double RESURF structure is also used for the terminating structure. A feature of the double RESURF structure is addition of a low concentration p− region on the surface of the end portion of the n-type region compared to the single RESURF structure. When a reverse potential is applied between a isolated n-type region and a p-substrate of the double RESURF structure, depletion layers expand from both the p− region on the surface region and the p-substrate in the end portion of the n-type region.
The following describes an example of a specific construction and operation of an integrated circuit having the double RESURF structure.
FIG. 9
is a plane view of an example of a construction of a conventional high voltage driver integrated circuit.
The high voltage driver of
FIG. 9
has the double RESURF structure. A high voltage IC chip
90
includes three regions
901
forming floating-potential-based circuits for a U-phase, a V-phase, and a W-phase of an upper arm and a region
902
forming a ground-potential-based circuit.
Each of the regions
901
forming the floating-potential-based circuits is surrounded by a high voltage junction terminating structure
903
.
FIG. 10
is a cross-sectional view showing a structure along a line B-B′ in the conventional integrated circuit of FIG.
9
.
FIG. 11
is a cross-sectional view showing a structure along a line C-C′ in the conventional integrated circuit of FIG.
9
. The conventional integrated circuit illustrated in
FIGS. 10 and 11
includes a region
901
forming a floating-potential-based circuit formed in an n-region
92
U-phase in the surface region of a p-substrate
910
and a p− region
902
forming a ground-potential-based circuit formed in an n-region
702
. The p− region
902
is formed in a surface region of a p+ region
801
.
Each of the n-region
92
and the n-region
702
contains various semiconductor devices composing a control circuit. As examples of such semiconductor devices,
FIGS. 10 and 11
show a P-MOS (P channel MOS transistor) and an N-MOS (N channel MOS transistor) in each of the n-regions.
A symbol Vcc in the n-region
702
indicates a wiring of a power supply of the lower arm (not shown). An electric potential of the wiring Vcc with respect to the ground potential GND is usually in a range from 10 to 20 volts, for example.
A high voltage junction terminating structure
903
is formed around the n-region
92
and the n-region
98
that is adjacent to the n-region
92
. The n-region
98
is occasionally formed simultaneously in a process forming the n-region
92
.
A symbol V
UL
in the n-region
92
indicates a base potential of the floating-potential-based circuit, and a symbol V
UH
indicates a power supply potential of the floating-potential-based circuit. The voltage of an upper arm power supply is given by V
UH
−V
UL
that is a potential difference between the potential V
UH
and the potential V
UL
. The voltage V
UH
−V
UL
is set to a value between 10 and 20 volts, for example.
A wiring at the base potential V
UL
connects to a midpoint of two IGBTs in upper and lower arms that are driven by the high voltage driver circuit. More specifically, the midpoint is the point at which an emitter of an upper arm IGBT and a collector of a lower arm IGBT join together. The base potential V
UL
changes rapidly in the switching process of the IGBT between 0 and 600 V for an IC of a withstand voltage of 600 V-class, or between 0 and 1,200 V for an IC of a withstand voltage of 1,200 V-class. A variation rate dV/dt of the potential V
UL
rises up to 10 to 20 kV/ps in some cases.
FIG. 9
shows a three phase driver IC, which has two other n-type regions for a V-phase and a W-phase having the floating-potential-based circuits on the p-substrate
910
as well as the n-region
92
for the U-phase. The base potentials VVL and VWL in these n-type regions for V- and W-phases also change rapidly in the switching process of the IGBTs like the potential V
UL
in the n-region
92
for the U-phase. Junction capacitance exists at each pn junction formed in the above-described conventional integrated circuit, which implies existence of a type of capacitor.
When a voltage with a rapidly changing waveform dV/dt is applied to this capacitor, a charging current or a displacement current C×dV/dt flows at a whole surface of the pn junction, where C is a capacitance of the capacitor. This charging current drives the parasitic transistors
911
and
912
shown in
FIGS. 10 and 11
, as described below. This may cause malfunction of the circuit and device destruction, which has been a problem with the conventional integrated circuit.
FIG. 12
is a cross-sectional view along the line B-B′ of
FIG. 9
showing the conventional integrated circuit, to which an example of a latch-up current is added.
FIG. 13
is a cross-sectional view along the line C-C

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