CMOS device with stressed sidewall spacers

Details CMOS device with stressed sidewall spacers CMOS device with stressed sidewall spacers

2005-09-08

2010-02-02

Soward, Ida M (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S327000, C257S335000, C257S336000, C257S344000, C257S900000, C257SE29266, C257SE29267, C257SE29268, C257SE29269, C257SE29278, C257SE29279

Reexamination Certificate

active

07655991

ABSTRACT:
Sidewall spacers on the gate of a MOS device are formed from stressed material so as to provide strain in the channel region of the MOS device that enhances carrier mobility. In a particular embodiment, the MOS device is in a CMOS cell that includes a second MOS device. The first MOS device has sidewall spacers having a first (e.g., tensile) type of residual mechanical stress, and the second MOS device has sidewall spacers having a second (e.g., compressive) type of residual mechanical stress. Thus, carrier mobility is enhanced in both the PMOS portion and in the NMOS portion of the CMOS cell.

REFERENCES:
patent: 4985744 (1991-01-01), Spratt et al.
patent: 5650340 (1997-07-01), Burr et al.
patent: 5696012 (1997-12-01), Son
patent: 5989986 (1999-11-01), Hsieh
patent: 6075262 (2000-06-01), Moriuchi et al.
patent: 6157064 (2000-12-01), Huang
patent: 6177319 (2001-01-01), Chen
patent: 6262445 (2001-07-01), Swanson et al.
patent: 6287988 (2001-09-01), Nagamine et al.
patent: 6306712 (2001-10-01), Rodder et al.
patent: 6399973 (2002-06-01), Roberds
patent: 6541343 (2003-04-01), Murthy et al.
patent: 6563152 (2003-05-01), Roberds et al.
patent: 6573172 (2003-06-01), En et al.
patent: 6713360 (2004-03-01), Jain et al.
patent: 6743684 (2004-06-01), Liu
patent: 6870179 (2005-03-01), Shaheed et al.
patent: 6906393 (2005-06-01), Sayama et al.
patent: 6939814 (2005-09-01), Chan et al.
patent: 7022561 (2006-04-01), Huang et al.
patent: 7052964 (2006-05-01), Yeo et al.
patent: 7053400 (2006-05-01), Sun et al.
patent: 7138309 (2006-11-01), Lee et al.
patent: 7193254 (2007-03-01), Chan et al.
patent: 7208362 (2007-04-01), Chidambaram
patent: 7259105 (2007-08-01), Kim
patent: 7265419 (2007-09-01), Minami
patent: 7288448 (2007-10-01), Orlowski et al.
patent: 7423283 (2008-09-01), Luo et al.
patent: 7429775 (2008-09-01), Nayak et al.
patent: 7528028 (2009-05-01), Liang et al.
patent: 2004/0104405 (2004-06-01), Huang et al.
patent: 2005/0040460 (2005-02-01), Chidambarrao et al.
patent: 2005/0136606 (2005-06-01), Rulke et al.
patent: 2005/0156237 (2005-07-01), Grudowski
patent: 2005/0247986 (2005-11-01), Ko et al.
patent: 2005/0260817 (2005-11-01), Kim
patent: 2005/0266639 (2005-12-01), Frohberg et al.
patent: 2005/0285187 (2005-12-01), Bryant et al.
patent: 2006/0009041 (2006-01-01), Iyer et al.
patent: 2006/0014350 (2006-01-01), Wang et al.
patent: 2006/0189167 (2006-08-01), Wang et al.
patent: 2006/0244074 (2006-11-01), Chen et al.
patent: 2006/0252194 (2006-11-01), Lim et al.
patent: 2006/0267106 (2006-11-01), Chao et al.
patent: 2007/0001217 (2007-01-01), Chen et al.
patent: 2007/0010073 (2007-01-01), Chen et al.
patent: 2007/0034963 (2007-02-01), Sudo
Yuhao Luo, et al. “Strain-Silicon CMOS using Etch-Stop Layer and Method of Manufacture”, U.S. Appl. No. 11/146,640, filed Jun. 7, 2005, 17pages, available from Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124.
Yuhao Luo, et al., “Semiconductor Device with Backfilled Isolation” U.S. Appl. No. 11/244,566, filed Oct. 6, 2005, 13 pages, available from Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124.
T. Ghani et al., “A 90nm High volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors”, IEEE, 2003, pp. 1-3, available from fahr.ghani@intel.com, or Intel Corporation (Santa Clara) Corporate Office, 2200 Mission College Blvd., Santa Clara, California 95052-8119.
Min Chin Chai, “90 nm Node CMOS Technology Comparison between Intel Corporation and Samsung Electronics”, pp. 1-6, May 8, 2003, available from Intel Corporation (Santa Clara) Corporate Office, 2200 Mission College Blvd., Santa Clara, California 95052-8119.
Brand et al., “Intel's 0.25 Micron, 2.0Volts Logic Process Technology”, pp. 1-9, available from Intel Corporation (Santa Clara) Corporate Office, 2200 Mission College Blvd., Santa Clara, California 95052-8119, Intel Technology Journal Q3'98.
B. P. R. Chidambaram et al., “35% Drive Current Imporvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS”, 2004 Sumposium on VLSI Technology Digest of Technical Papers, pp. 48-49, available from Texas Instruments, MS 3739, 13560 N. Central Expressway, Dallas, TX 75243.
Luo, Y. et al., “Enhancement of CMOS Performance by Process-Induced Stress”, IEEE Transactions on Seminconductors Manufacturing, vol. 18, No. 1, Feb. 2005, pp. 63-68.
U.S. Appl. No. 11/095,814, Nayak et al.,“Method of Fabricating Strain-Silicon CMOS”, filed Mar. 31, 2005, Xilinx, Inc. 2100 Logic Drive, San Jose, California 95124.
U.S. Appl. No. 11/221,507, Nayak, D.K. et al., “CMOS Device With Stressed Sidewall Spacers”, filed Sep. 8, 2005, Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 12/200,851, filed Aug. 28, 2008, Luo et al. Xilinx, Inc. 2100 Logic Drive, San Jose, California.
U.S. Appl. No. 12/200,871, filed Aug. 28, 2008, Nayak et al., Xilinx, Inc. 2100 Logic Drive, San Jose, California.
U.S. Appl. No. 11/146,640, filed Jun. 7, 2005, Luo et al.
Pidin, S. et al., “A Novel Strain Enchanced CMOS Architecture Using Selectively Deposited High Tensile and High Compressive Silicon Nitride Films”, Jan. 2004, pp. 1-4, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Thompson, S. et al., “A 90 nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 Layor of Cu Interconnects, Low κ ILD and 1 um2SRAM Cell”, 2002, pp. 1-4, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.

Affiliated with

Also associated with

Rating

CMOS device with stressed sidewall spacers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS device with stressed sidewall spacers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS device with stressed sidewall spacers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4232250