Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-12-12
2008-08-26
Lindsay, Jr., Walter L (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S390000, C257S354000, C257SE29263
Reexamination Certificate
active
07417283
ABSTRACT:
A CMOS device having dual polycide gates is formed by first providing a silicon substrate, which is divided into a cell area and a peripheral circuit area and has a device isolation layer, a P-well, and a N-well in the peripheral circuit area. The n+ polycide gate at the P-well and the p+ polycide gate at the N-well are formed. An interlayer dielectric layer is formed on the resultant of the silicon substrate having the n+ polycide gate and the p+ polycide gate. A first bit-line contact hole for exposing the n+ polycide gate is formed, and a second bit-line contact hole for exposing the p+ polycide gate is formed. Bit-lines with a bridge structure on the interlayer dielectric layer is formed. The bit-lines simultaneously contact the n+ polycide gate and the p+ polycide gate through the first and second bit-line contact holes.
REFERENCES:
patent: 5292677 (1994-03-01), Dennison
patent: 5444018 (1995-08-01), Yost et al.
patent: 5643819 (1997-07-01), Tseng
patent: 5648291 (1997-07-01), Sung
patent: 5686337 (1997-11-01), Koh et al.
patent: 5705438 (1998-01-01), Tseng
patent: 5780338 (1998-07-01), Jeng et al.
patent: 5793086 (1998-08-01), Ghio et al.
patent: 6001717 (1999-12-01), Lien
patent: 6010933 (2000-01-01), Cherng
patent: 6083790 (2000-07-01), Lin et al.
patent: 6127716 (2000-10-01), Morizuka et al.
patent: 6171970 (2001-01-01), Xing et al.
patent: 6197653 (2001-03-01), Khamankar et al.
patent: 6271073 (2001-08-01), Roberts
patent: 6432760 (2002-08-01), Kothandaraman et al.
patent: 6512245 (2003-01-01), Ikeda et al.
patent: 6617631 (2003-09-01), Huang
patent: 7253465 (2007-08-01), Yamamoto et al.
patent: 2002/0047156 (2002-04-01), Kim
patent: 2002/0127867 (2002-09-01), Lee
patent: 2004/0232497 (2004-11-01), Akiyama et al.
patent: 2005/0139884 (2005-06-01), Lane
patent: 2007/0004119 (2007-01-01), Chun
patent: 10-2000-0002347 (2000-01-01), None
patent: 10-2002-0073642 (2002-09-01), None
patent: 10-2004-0090476 (2004-10-01), None
Korean Patent Gazette, Mar. 29, 2007.
Hynix / Semiconductor Inc.
Ladas & Parry LLP
Lindsay, Jr. Walter L
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