CMOS devices with graded silicide regions

Details CMOS devices with graded silicide regions CMOS devices with graded silicide regions

2006-08-01

2009-06-09

Prenty, Mark (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S408000

Reexamination Certificate

active

07545006

ABSTRACT:
A semiconductor device includes a semiconductor substrate, a gate stack overlying the semiconductor substrate, a spacer on a sidewall of the gate stack, a lightly doped source/drain (LDD) region adjacent the gate stack, a deep source/drain region adjoining the LDD region, and a graded silicide region on the deep source/drain region and the LDD region. The graded silicide region includes a first portion having a first thickness and a second portion adjoining the first portion and having a second thickness substantially less than the first thickness. The second portion is closer to a channel region than the first portion.

REFERENCES:
patent: 6548877 (2003-04-01), Yang et al.
patent: 7309901 (2007-12-01), Chen et al.
patent: 7423283 (2008-09-01), Luo et al.
patent: 2006/0255413 (2006-11-01), Oh et al.
Yoshitomi, T., et al., “High Performance of Silicided Silicon-Sidewall Source and Drain(S4D) Structure,” IEEE Transactions on Electron Devices, vol. 45, No. 6, Jun. 1998, pp. 1295-1299.

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