CMOS ESD protection structure

Details CMOS ESD protection structure CMOS ESD protection structure

1995-01-05

1995-08-08

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257357, 257536, H01L 2702

Patent

active

054401631

ABSTRACT:
A semiconductor integrated circuit device including a CMOS inverter which can be prevented to be destroyed due to electrostatic charges. First and second contact layers are formed just above the source and drain regions of an n-channel MOS transistor, respectively, between a first interlayer insulator film having first contact holes and a second interlayer insulator film having second contact holes. The first and second contact layers are made of material higher in electric resistance than metal, for example metal silicides. The source and drain regions of the n-channel MOS transistor are respectively contacted through the first contact holes with the first and second contact layers which are respectively contacted through the second contact holes with a metal ground wiring layer and a metal output wiring layer. The first and second interlayer insulator films have third contact holes penetrating both interlayer insulator films. The source and drain regions of a p-channel MOS transistor are electrically connected through third contact holes to a metal power source wiring layer and the metal output wiring layer, respectively.

REFERENCES:
patent: 4931845 (1990-06-01), Ema
patent: 5060037 (1991-10-01), Rountree
patent: 5241206 (1993-08-01), Lee et al.
Kueing-Long Chen, "Effects of Interconnect Process and Snapback Voltage on the ESD Failure Threshold of NMOS Transistors", Dec. 1988 EOS/ESD Symposium Proceedings, Texas Instruments Incorporated, Dallas, Tex., pp. 212-219.

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