CMOS device with improved wiring density

Details CMOS device with improved wiring density CMOS device with improved wiring density

1999-03-30

2000-06-27

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257369, 438199, 438219, H01L 2976, H01L 2994, H01L 31062, H01L 31113, H01L 31119

Patent

active

060810165

ABSTRACT:
A method of manufacturing a semiconductor device comprising the following steps: forming first, second, and third wiring layers on a semiconductor substrate; forming first, second, and third cover dielectric layers for covering these wiring layers; forming a first impurity diffusion layer of a P type and a second impurity diffusion layer of an N type in an active region, and forming a third impurity diffusion layer of a P type and a fourth impurity diffusion layer cf an N type in an active region; self-alignably forming a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer, and self-alignably forming a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer; in an interlayer dielectric layer, self-alignably forming a first contact hole by using the first and third cover dielectric layers as masking layers, and self-alignably forming a second contact hole by using the second cover dielectric layer as a masking layer; and forming fourth and fifth wiring layers in these contact holes, respectively.

REFERENCES:
patent: 5254874 (1993-10-01), Malwah
patent: 5294822 (1994-03-01), Verrett
patent: 5298782 (1994-03-01), Sundaresan
patent: 5309010 (1994-05-01), Kitajima
patent: 5619056 (1997-04-01), Kuriyama et al.
patent: 5880502 (1999-03-01), Lee et al.
patent: 5981320 (1999-11-01), Lee

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