CMOS devices having minimized drain contact area

Details CMOS devices having minimized drain contact area CMOS devices having minimized drain contact area

1996-08-09

1998-11-03

Wallace, Valencia Martin

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257351, 257357, 257369, 257371, 257374, 437 56, 437 57, 437 58, 437 67, H01L 2976, H01L 2994, H01L 2362

Patent

active

058313052

ABSTRACT:
There are disclosed a semiconductor device and a method for fabrication thereof. The semiconductor device comprises an insulating film for well isolation which electrically insulates N-well from P-well, the drain electrode of PMOS and the drain electrode of NMOS being adjacent to the trench fox well isolation, and a conductive wire filling one contact hole which interconnects the drain electrodes of N-well with those of P-well. The semiconductor device is very reduced in size, and thus, high integration thereof can be achieved.

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patent: 5362981 (1994-11-01), Sato et al.
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