CMOS device using additional implant regions to enhance ESD...

Details CMOS device using additional implant regions to enhance ESD... CMOS device using additional implant regions to enhance ESD...

2000-09-05

2004-03-09

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S338000

Reexamination Certificate

active

06703663

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to CMOS devices with enhanced ESD performance.
2. Description of Related Art
Junction leakage and junction short circuits to the substrate are more and more likely to occur in advanced technology devices as the dimensions of the devices forming those circuits become smaller and smaller.
U.S. Pat. No. 5,514,611 of Kim et al. for “Method for Manufacturing a Semiconductor Memory Device Having a Read-Only Memory Cell” shows a S/D (source/drain) structure with three I/I (Ion Implanted) doped regions.
U.S. Pat. No. 5,559,352 of Hsue for “ESD Protection Improvement” shows an ESD circuit with three I/I doped regions.
U.S. Pat. No. 5,493,142 of Randazzo et al. for “Input/Output Transistors with Optimized ESD Protection” has a lightly doped region disposed near the gate and the surface of the substrate. A sidewall oxide layer is selectively etched to extend laterally from a gate by a significant amount. The sidewall oxide layer is also etched on an opposite side of the gate and may extend laterally an appreciable amount in that direction. Heavily doped S/D regions are implanted in the substrate. The extent of the sidewall oxide, and thus the lightly doped regions separating the gate from the drain and source, can be tailored to optimize ESD protection and performance characteristics for a given application by defocusing snapback conduction.
U.S. Pat. No. 5,130,760 of Matzen et al. for “Bidirectional Surge Suppressor Zener Diode Circuit With a Guard Ring” describes a semiconductor device incorporating doped regions of a substrate and epitaxial layers which result in a dual Zener diode arrangement having the Zener diodes associated in an opposite polarity arrangement.
SUMMARY OF THE INVENTION
A semiconductor memory device is formed on a semiconductor substrate with an N-well and a P-well. The combination of a gate oxide layer and a gate electrode layer are formed over a substrate and patterned into gate electrode stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. P− lightly doped source/drain regions are formed in the N-well. N− lightly doped source/drain regions are formed in the P-well. Spacers are formed on the sidewalls of the gate electrode stacks. Heavily doped P++ regions self-aligned with the gate electrode were formed below future P+ source/drain sites to be formed self-aligned with the spacers in the N-well, and heavily doped N++ regions self-aligned with the gate electrode were formed below future N+ source/drain sites to be formed self-aligned with the spacers in the P-well. Deep N− lightly doped source/drain regions were formed in the N-well directly below the P++ regions. Deep P− lightly doped source/drain regions were formed in the P-well directly below the N++ regions.
The N+ type source/drain regions were formed in the P-well in the source/drain sites. The P+ type source/drain regions were formed in the N-well in the source/drain sites. Refractory metal silicide layers were formed over the gate electrode layers.
The refractory metal silicide layers were formed over the source/drain regions, P−/N++ junctions were formed below the N+ source/drain regions in the P-well, and N−/P++ junctions were formed below the P+ source/drain regions in the N-well.
The deep lightly doped N− and P− regions are formed to a depth from about 0.2 &mgr;m to about 0.3 &mgr;m below the surface of the substrate, and the counterdoped N++ and P++ regions are formed to a depth from about 0.1 &mgr;m to about 0.2 &mgr;m below the surface of the substrate.
Preferably, the deep lightly doped N− and P− regions are formed to a depth from about 0.2 &mgr;m to about 0.3 &mgr;m below the surface of the substrate, with a concentration of phosphorus, P
31
, dopant in the N− regions from about 1 E 17 atoms/cm
3
to about 1 E 18 atoms/cm
3
.
There is a concentration of boron, B, dopant in the P− regions from about 1 E 17 atoms/cm
3
to about 1 E 18 atoms/cm
3
The counterdoped N++ and P++ regions are formed to a depth from about 0.1 &mgr;m to about 0.2 &mgr;m below the surface of the substrate.
There is a concentration of phosphorus, P
31
, or arsenic, As, dopant in the N++ regions from about 5 E 20 atoms/cm
3
to about 1 E 21 atoms/cm
3
and a concentration of boron, B, dopant in the P++ regions from about 5 E 20 atoms/cm
3
to about 1 E 21 atoms/cm
3
.
The S/D regions are formed with a concentration of arsenic, As, dopant in the N+ regions from about 1 E 20 atoms/cm
3
to about 5 E 20 atoms/cm
3
and a concentration of boron, B, dopant in the P+ regions from about 1 E 20 atoms/cm
3
to about 5 E 20 atoms/cm
3
.
The lightly doped S/D regions are formed with a concentration of phosphorus, P
31
, or arsenic, As, dopant in the N− regions from about 1 E 18 atoms/cm
3
to about 1 E 20 atoms/cm
3
and a concentration of boron, B, dopant in the P− regions from about 1 E 18 atoms/cm
3
to about 1 E 20 atoms/cm
3
.


REFERENCES:
patent: 5130760 (1992-07-01), Matzen et al.
patent: 5493142 (1996-02-01), Randazzo et al.
patent: 5514611 (1996-05-01), Kim et al.
patent: 5559352 (1996-09-01), Hsue et al.
patent: 5677224 (1997-10-01), Kadosh et al.
patent: 6043129 (2000-03-01), Choi et al.
patent: 6051471 (2000-04-01), Gardner et al.
patent: 6150687 (2000-11-01), Noble et al.

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