CMOS device with zero soft error rate

Details CMOS device with zero soft error rate CMOS device with zero soft error rate

2006-10-12

2010-10-26

Bryant, Kiesha R (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S327000, C257S369000, C257S471000, C257SE27068

Reexamination Certificate

active

07821075

ABSTRACT:
A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.

REFERENCES:
patent: 4864382 (1989-09-01), Aoki et al.
patent: 5124770 (1992-06-01), Umemoto et al.
patent: 6255704 (2001-07-01), Iwata et al.
patent: 6271105 (2001-08-01), Kwon et al.
patent: 6303479 (2001-10-01), Snyder
patent: 6420763 (2002-07-01), Yamashita et al.
patent: 7230303 (2007-06-01), Liao
patent: 7521765 (2009-04-01), Tsutsumi et al.
patent: 2003/0235936 (2003-12-01), Snyder et al.
patent: 2004/0041226 (2004-03-01), Snyder et al.
patent: 2005/0062071 (2005-03-01), Matsuzawa et al.
patent: 2005/0079668 (2005-04-01), Jung
patent: 2006/0125040 (2006-06-01), Levin et al.
J. Kedzierski et al., “Complementary silicide source/drain thin body MOSFETs for the 20 mm gate length regime”,IEDM, 2000, pp. 57-60.
E. DuBois et al., Low Schottky barrier source/drain for advanced MOS architecture: device design and maSolid State Electronics, 2002, pp. 997-1004.
J. Guo et al., IEEE Transaction on Electronic Devices, 2002, pp. 1897-1902.
K. Ikeda et al., IEEE Electronic Device Letters, 2002, pp. 670-672.
M. Tao et al., Applied Physics Letters, 2003, pp. 2593-2595.
Ng, Wai Tung and Salama, Andre T., “A CMOS-Compatible Complementary SINFET HVIC Process”,IEEE Transactions on Electronic Devices, vol. 38, Aug. 1991, No. 8, pp. 1935-1942.
Kenichi, Osada, et al., “Analysis of SRAM Neutron-Induced Errors Based on Consideration of Both Charge-Collection and Parasitic-Bipolar Failure Modes”, IEEE 2004 Custom Integrated Circuits Conference, p. 357.
C. M. Hsieh, et al., “A Field-funneling Effect on the Collection of Alpha-Particle-Generated Carriers in Silicon Devices”, IEEE Electron Device Letters, V. 2, No. 4, p. 103, 1981.
“A CMOS-Compatabile Complementary SINFET HVIC Process”, by Wai Tung Ng and C. Andre T. Salama,IEEE Transactions on Electron Devices, vol. 38, Aug. 1991, No. 8, pp. 1935-1942.
Gasiot et al., “Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm CMOS SRAMs and Its Dependence on Well Engineering”, IEEE Transaction on Nuclear Science, Dec. 2007, pp. 2468-2473, vol. 54, No. 6.
Hutson et al., “The Effects of Scaling and Well and Substrate Contact Placement on Single Event Latchup in Bulk CMOS Technology”, “RADECS 2005 Proceedings”, 2005, pp. PC24.1-PC24.5.
Narasimham et al., “Effects of Guard Bands and Well Contracts in Mitigating Long SETs in Advanced CMOS Process”, “IEEE Transactions on Nuclear Science”, Jun. 2008, pp. 1708-1713, vol. 55, No. 3.
Olson et al., “Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Well Contacts in 130 nm and 90 nm CMOS Technology”, “IEEE Transactions on Nuclear Science”, Aug. 2007, pp. 894-897, vol. 54, No. 4.
Puchner et al., “Alpha-Particle SEU Performance of SRAM With Triple Well”, “IEEE Transactions on Nuclear Science”, Dec. 2004, pp. 35253528, vol. 51, No. 6.
Seifert et al., “Multi-Cell Upset Probabilities of 45 nm High-k + Metal Gate SRAM Devices in Terrestrial and Space Enviroments”, “IEEE 46th Annual International Reliability Physics Symposium, Phoenix, 2008”, 2008, pp. 181-186.

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