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Architecture, system and method for compressing repair data...

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Area efficient differential EEPROM cell with improved data...

Static information storage and retrieval – Read/write circuit – Particular read circuit
Reexamination Certificate

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Area efficient first-in first-out circuit

Static information storage and retrieval – Read/write circuit – Serial read/write
Reexamination Certificate

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Area efficient global row redundancy scheme for DRAM

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Area efficient method for programming electrical fuses

Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate

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Area-efficient memory built-in-self-test circuitry with...

Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate

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Arithmetic circuit integrated with a variable resistance...

Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
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Arrangement and method of ascertaining memory addresses which ha

Static information storage and retrieval – Read/write circuit
Patent

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Arrangement for extraction and receiving data for a refreshable

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Patent

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Arrangement for the automatic reconfiguration of an intact equip

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Arrangement of bitline boosting capacitor in semiconductor...

Static information storage and retrieval – Read/write circuit – For complementary information
Reexamination Certificate

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Arrangement of redundant cell array for semiconductor memory dev

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Arrangement with a memory for storing data

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Array architecture and operating methods for digital...

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Array block level redundancy with steering logic

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Array containing charge storage and dummy transistors and...

Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate

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Array data input latch and data clocking scheme

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Array discharge for biased array

Static information storage and retrieval – Read/write circuit – Precharge
Patent

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Array driver

Static information storage and retrieval – Read/write circuit – Precharge
Patent

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Array redundancy supporting multiple independent repairs

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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