Arithmetic circuit integrated with a variable resistance...

Details Arithmetic circuit integrated with a variable resistance... Arithmetic circuit integrated with a variable resistance...

2007-05-22

2007-05-22

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including specified plural element logic arrangement

C365S163000, C365S148000, C365S225700, C326S113000, C326S112000, C326S104000, C326S038000

Reexamination Certificate

active

11186207

ABSTRACT:
An arithmetic circuit is provided having a compact and high-speed logic-in-memory wherein various operations are performed. The arithmetic circuit includes a memory element having a variable resistance element R in which the state of resistance changes reversibly between the state of high resistance and the state of low resistance by applying voltages with different polarities between one electrode and the other electrode, and at least one transistor of MRD, MRS, MW1and MW2connected respectively to both ends of the memory element; wherein data is stored in the memory element, the operation for the external data X, W, Y1and Y2input through any of the transistors is performed by applying potential to each of the ends of the memory element through the transistors MRD, MRS, MW1, and MW2, and a result of the operation is output from the memory element.

REFERENCES:
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patent: 2006/0092691 (2006-05-01), Shiimoto et al.
Kimura et al., “Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition”, Proceedings of 32nd IEEE International Symposium on Multiple-Valued Logic, May 15-18, 2002, pp. 161-166.

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