Array data input latch and data clocking scheme

Details Array data input latch and data clocking scheme Array data input latch and data clocking scheme

2008-07-02

2010-10-12

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S154000

Reexamination Certificate

active

07813189

ABSTRACT:
A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues.

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