Area efficient first-in first-out circuit

Details Area efficient first-in first-out circuit Area efficient first-in first-out circuit

2008-05-13

2010-02-09

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S227000

Reexamination Certificate

active

07660178

ABSTRACT:
A FIFO memory having an available capacity of no more than N words deep by M bits wide. A write port receives data to store in the FIFO memory, and a read port provides the data stored in the FIFO memory. X memories store the data, where each of the X memories has a size of N/X by M. Control logic receives the data from the write port, writes the data into at least one of the X memories in a serial write manner, reads the data from at least one of the X memories in a serial read manner, and provides the data to the read port. The control logic also disables power to selected ones of the X memories when they are not being written to or read from. The FIFO memory is configured to both read and write the data at a given time to a given one of the X memories.

REFERENCES:
patent: 4833651 (1989-05-01), Seltzer et al.
patent: 4833655 (1989-05-01), Wolf et al.
patent: 4912680 (1990-03-01), Masaki et al.
patent: 5274589 (1993-12-01), Koshizuka
patent: 6144604 (2000-11-01), Haller et al.

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