Area-efficient memory built-in-self-test circuitry with...

Details Area-efficient memory built-in-self-test circuitry with... Area-efficient memory built-in-self-test circuitry with...

2011-08-23

2011-08-23

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S230030, C365S230080

Reexamination Certificate

active

08004915

ABSTRACT:
An integrated circuit is provided with built-in-self test circuitry. The integrated circuit may have multiple blocks of memory. The memory may be tested using the built-in-self test circuitry. Each memory block may include a satellite address generator that is used in generating test addresses for the memory blocks. Each memory block may also include failure analysis logic and output response analyzer logic. Stalling logic may be used to individually stall memory block testing on a block-by-block basis during memory tests. Address buffer circuitry such as first-in-first-out buffers may be used to provide randomized memory addresses during testing.

REFERENCES:
patent: 6910155 (2005-06-01), Ku
patent: 7017094 (2006-03-01), Correale
patent: 7188274 (2007-03-01), Nadeau-Dostie
patent: 7266028 (2007-09-01), Ghosh Dastidar
patent: 2003/0063517 (2003-04-01), Jain
patent: 2009/0116321 (2009-05-01), Shirur et al.

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