Array discharge for biased array

Static information storage and retrieval – Read/write circuit – Precharge

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Details

365104, 365226, G11C 700

Patent

active

047978570

ABSTRACT:
A discharge circuit for discharging bit lines of an array of semiconductor memory cells in which the array of bit lines are biased from a single bias line. The discharge circuit includes a discharge switch coupled to the bias line for discharging the bit lines and the bias line and a control circuit coupled to the discharge switch operative to turn on the discharge switch in response to the voltage on the bias line rising above a first predetermined level and then to turn off the discharge switch in response to the voltage on the bias line falling below a second predetermined level.

REFERENCES:
patent: 4319344 (1982-03-01), Heuber et al.
patent: 4321489 (1982-03-01), Higuchi et al.
patent: 4651302 (1987-03-01), Kimmel et al.

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