Array containing charge storage and dummy transistors and...

Details Array containing charge storage and dummy transistors and... Array containing charge storage and dummy transistors and...

2002-12-23

2004-10-19

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185110, C365S185200

Reexamination Certificate

active

06807119

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed generally to semiconductor devices and methods of fabrication and more particularly to an array of charge storage transistor array and method of operation.
BACKGROUND OF THE INVENTION
Charge storage transistors are transistors which contain a charge storage region. These transistors may be used in memory devices, such as in electrically erasable programmable memories (EEPROM). The charge storage transistors may be programmed by Fowler-Nordheim (FN) tunneling or by channel hot electron (CHE) injection.
BRIEF SUMMARY OF THE INVENTION
A preferred embodiment of the present invention provides a method of operating an array of transistors, comprising providing the array of transistors, comprising a plurality of charge storage transistors, and a plurality of dummy transistors interspersed with the plurality of charge storage transistors. Each of the plurality of the dummy transistors is made using same photolithographic masking steps as each of the plurality of the charge storage transistors. The method further comprises at least one of programming and erasing the array of transistors, and reading the plurality of charge storage transistors but not the plurality of dummy transistors of the array of transistors.
Another preferred embodiment of the present invention provides a semiconductor device, comprising an array of transistors comprising a plurality of charge storage transistors, and a plurality of dummy transistors interspersed with the plurality of charge storage transistors. Each of the plurality of the dummy transistors is made using same photolithographic masking steps as each of the plurality of the charge storage transistors. The device further comprises a first means for (i) at least one of programming and erasing the array of transistors, and (ii) reading the plurality of charge storage transistors but not the plurality of dummy transistors of the array of transistors.
Another preferred embodiment of the present invention provides a semiconductor device, comprising an array of transistors comprising a plurality of charge storage transistors, and a plurality of dummy transistors interspersed with the plurality of charge storage transistors. Each of the plurality of the dummy transistors is made using same photolithographic masking steps as each of the plurality of the charge storage transistors. The device further comprises a peripheral programming circuitry operable to (i) at least one of program and erase the array of transistors, and (ii) read the plurality of charge storage transistors but not the plurality of dummy transistors of the array of transistors.


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An Asymmetrical Lightly Doped Source Cell for Virtual Ground High-Density EPROM's Kuniyoshi Yoshikawa, Member, IEEE, IEEE Transactions on Electron Devices, vol. 37, No. 4, Apr. 1990.

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