Arrangement of bitline boosting capacitor in semiconductor...

Details Arrangement of bitline boosting capacitor in semiconductor... Arrangement of bitline boosting capacitor in semiconductor...

2001-06-11

2002-08-20

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

For complementary information

C365S205000, C365S207000, C365S208000

Reexamination Certificate

active

06438042

ABSTRACT:

This application relies for priority upon Korean Patent Application No.
2001-347,
filed on Jan. 4, 2001, the contents of which are incorporated herein by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to an arrangement of a boosting capacitor that is used in a dynamic random access memory (DRAM).
BACKGROUND OF THE INVENTION
A part of a DRAM is illustrated in FIG.
1
. In a memory cell
10
, one end of a capacitor
11
is connected to a bitline BLB through a charge transfer transistor
12
. In a memory cell
20
, one end of a capacitor
21
is connected to a bitline BL through a charge transfer transistor
22
. A plate potential Vp is applied to the other ends of the capacitors
11
and
21
, respectively. Gates of the charge transfer transistors
12
and
22
are coupled to wordlines WL
0
and WL
1
, respectively. When information of a memory cell (e.g., cell
10
) is read out, the bitlines BL and BLB are set to a precharge potential. If the charge transfer transistor
12
is turned on for a predetermined time, a potential difference between the bitlines BL and BLB is amplified by a sense amplifier
30
.
With scaling-down of circuit devices and lowering of operation voltages, potential change of a bitline has been attenuated in a read operation. Moreover, a ratio of a current leakage of a capacitor to an electric charge held at the capacitor increases. A current leakage occurring when a higher level “H” is held at a capacitor is greater than that occurring when a lower level “L” is held thereat. If the potential change is so small, a sense amplifier suffers from erroneous operations to output error data. Thus, an efficient margin is needed for the potential change to amplify a potential difference between bitlines, without the erroneous operations of the sense amplifier.
Source and drain of a MOS transistor
31
whose gate is coupled to a dummy wordline DWL
0
are connected to a bitline BLB, while those of a MOS transistor
32
whose gate is coupled to a dummy wordline DWL
1
are connected to a bitline BL. Each of the MOS transistors
31
and
32
acts as a capacitor, which is called a “bitline boosting capacitor”. When the information of the memory cell
10
is read out, a potential of the wordline WL
0
rises up to high level, to turn on the charge transfer transistor
12
. At the same time, a potential of the dummy wordline DWL
0
transitions from 0V to high level of a power supply voltage to complement a positive charge for the bitline BLB. Compensation of the attenuated potential change can be made through bitline boosting capacitors
31
,
32
, and a stable data sense margin can be secured therethrough.
Semiconductor memory devices with such a boosting capacitor are disclosed in U.S. Pat. No. 5,255,235 and U.S. Pat. No. 5,768,204.
In semiconductor memory devices, not only improvement of a data sense margin but also decrease in a chip size become significant factors of product competitiveness. And, significant factors to decrease in the chip size are achievement of a minute circuit linewidth and an optimal circuit arrangement. As described above, decrease in a chip size is inevitable with the use of a bitline boosting capacitor for improving a data sense margin. In order to suppress increase in the chip size with the use of the boosting capacitor, a method of efficiently arranging the bitline boosting capacitor in a limited area is required.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a semiconductor memory device with a boosting capacitor which is efficiently arranged.
According to an aspect of the present invention, a semiconductor memory device includes a memory cell array having a first bitline, a second bitline parallel with the first bitline, and memory cells connected to the first and second bitlines. A sense amplifier circuit senses a potential difference between the first and second bitlines. A first isolation transistor has a source region, a drain region, and a gate, and electrically connects/isolates the first bitline to/from the sense amplifier circuit. A second isolation transistor has a source region, a drain region, and a gate, and electrically connects/isolates the second bitline to/from the sense amplifier circuit. A MOS transistor has a source region and a gate, and is used as a boosting capacitor. The source region of the MOS transistor is formed such that it is shared with one of the source regions of the first and second isolation transistors. This saves, space, without compromising performance.


REFERENCES:
patent: 5701268 (1997-12-01), Lee et al.
patent: 6137737 (2000-10-01), Mullarkey et al.
patent: 6226207 (2001-05-01), Suh
patent: 6246604 (2001-06-01), Lowrey

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