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Memory units with normal and bit select write modes

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent

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Memory using a single-node data, address and control bus

Static information storage and retrieval – Read/write circuit
Reexamination Certificate

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Memory using a single-node data, address and control bus

Static information storage and retrieval – Read/write circuit
Reexamination Certificate

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Memory using undecoded precharge for high speed data sensing

Static information storage and retrieval – Read/write circuit – Including signal comparison
Patent

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Memory voltage generating circuit

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate

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Memory with a bit line block and/or a word line block for...

Static information storage and retrieval – Read/write circuit – Signals
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Memory with a bit line block and/or a word line block for...

Static information storage and retrieval – Read/write circuit – Signals
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Memory with a combined global data line load and multiplexer

Static information storage and retrieval – Read/write circuit – Multiplexing
Patent

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Memory with a memory cell comprising a MOS transistor with...

Static information storage and retrieval – Read/write circuit
Reexamination Certificate

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Memory with a memory cell comprising a MOS transistor with...

Static information storage and retrieval – Read/write circuit
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Memory with a selectable data width and reduced decoding logic

Static information storage and retrieval – Read/write circuit – Sipo/piso
Patent

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Memory with a temperature sensor, dynamic memory and memory...

Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate

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Memory with a variable impedance bit line load circuit

Static information storage and retrieval – Read/write circuit – For complementary information
Patent

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Memory with adjustable access time

Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate

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Memory with an optimized setting of precharge times

Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate

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Memory with auto refresh to designated banks

Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate

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Memory with bit line discharge circuit elements

Static information storage and retrieval – Read/write circuit – Accelerating charge or discharge
Patent

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Memory with column redundancy and localized column redundancy co

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory with compensation for voltage, temperature, and processin

Static information storage and retrieval – Read/write circuit – Signals
Patent

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Memory with configuration RAM

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent

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