Static information storage and retrieval – Read/write circuit – Multiplexing
Patent
1994-03-28
1995-12-12
Lane, Jack A.
Static information storage and retrieval
Read/write circuit
Multiplexing
365177, 365190, 365208, 36523003, 36523006, G11C 700, G11C 11419
Patent
active
054756359
ABSTRACT:
A combined global data line load and multiplexer comprises a decoder, a bias generator circuit, at least one output signal line pair, and a plurality of switching portions. The decoder provides a plurality of select signals in response to a portion of an address, each select signal provided at either a logic high voltage or at a logic low voltage. For example, a X4 memory internally organized X8 uses one extra address bit to select between two sets of four global data line pairs to provide as outputs. The bias generator circuit provides a bias signal at a voltage between the logic high and the logic low voltages. The output signal lines are each coupled through a respective resistor to a power supply voltage terminal. Each switching portion provides substantially a differential current between corresponding global data lines to corresponding output signal lines in response to the bias voltage exceeding a voltage of a corresponding select signal.
REFERENCES:
patent: 4314359 (1982-02-01), Kato et al.
patent: 4663741 (1987-05-01), Reinschmidt et al.
patent: 4866674 (1989-09-01), Tran
patent: 4928268 (1990-05-01), Nogle et al.
patent: 4984196 (1991-01-01), Tran et al.
patent: 5043945 (1991-08-01), Bader
Matsui, et al, "High-Speed SRAMs", 1989 IEEE Solid State Circuits Conference, pp. 38-39.
Tran et al, "An 8ns BiCMOS 1Mb ECL SRAM with a Configurable Memory Array Size", 1898 IEEE Solid State Circuit Conference, pp. 36-37.
Kertis et al, "A 12ns 256K BiCMOS SRAM", 1989 IEEE Solid State Circuits Conference, pp. 186-187.
Burnett and Hu, "Hot-Carrier Degradation in Bipolar Transistors at 300 and 110 K-Effect on BiCl Inverter Performance"< IEEE Transactions on Electron Devices, vol. 37, No. 4, Apr. 1990, p. 11.
Lane Jack A.
Motorola Inc.
Polansky Paul J.
LandOfFree
Memory with a combined global data line load and multiplexer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory with a combined global data line load and multiplexer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory with a combined global data line load and multiplexer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1365769