Memory with a memory cell comprising a MOS transistor with...

Details Memory with a memory cell comprising a MOS transistor with... Memory with a memory cell comprising a MOS transistor with...

2006-12-08

2008-09-23

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

C365S185010, C365S185090

Reexamination Certificate

active

07428175

ABSTRACT:
A dynamic random access memory (DRAM) including memory cells distributed in rows and in columns, each memory cell comprising a MOS transistor with a floating body, the memory comprising circuitry for writing a datum into a determined (i.e. selected) memory cell belonging to a determined (i.e. selected) row and to a determined (i.e. selected) column, wherein the write circuitry comprises circuitry capable of bringing the drains of the memory cells of the determined column to a voltage V1; circuitry capable of bringing the sources of the memory cells of the determined row to a voltage V2; and circuitry capable of bringing the drains of the memory cells of the columns other than the determined column and the sources of the memory cells of the rows other than the determined row to a voltage V3, voltages V1, V2, and V3being such that |V1−V2|>|V3−V2| and (V1−V2)×(V3−V2)>0.

REFERENCES:
patent: 7212434 (2007-05-01), Umezawa
patent: 2004/0228168 (2004-11-01), Ferrant et al.
patent: 31 38950 (1981-09-01), None

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