Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1983-08-31
1986-08-05
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365200, 365230, G11C 700
Patent
active
046047271
ABSTRACT:
A memory including various selectively configurable peripherals which provide on-chip low-level control features and a configuration RAM storing bits which both provide unclocked full logic-level outputs to control the selectively configurable peripherals and can also be accessed and read out. That is, each cell in the configuration RAM has two output modes: a digital continuous output, which is provided as a continuous control signal to various peripheral circuits and a selectable analog output which is used to read the information stored in the configuration RAM.
REFERENCES:
patent: 4390946 (1983-06-01), Lane
Chatterjee Pallab K.
Gallia James D.
Mahant-Shetti Shivaling S.
Shah Ashwin H.
Groover III Robert
Popek Joseph A.
Sharp Melvin
Sorensen Douglas A.
Texas Instruments Incorporated
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