Memory with an optimized setting of precharge times

Details Memory with an optimized setting of precharge times Memory with an optimized setting of precharge times

2000-04-21

2002-07-23

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S191000, C365S230020

Reexamination Certificate

active

06424580

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 99-05328, filed Apr. 23, 1999, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to memory devices, and more specifically to a method for optimizing memory read cycles of memory devices.
2. Description of Related Art
Generally, a read operation on a memory provides data on bit lines at an unknown time after a read control signal. The bit lines must be precharged before each read operation and, when two readings are performed in a row, the precharge necessary for the second reading must be started after the end of the first reading, that is, at an unknown time after the signal controlling the first reading.
FIG. 1
schematically shows a memory
1
formed of memory cells
2
arranged in rows and columns. The cells of each row are selected by a respective row line
3
, and the cells of each column are accessible in the read mode by a respective pair of complementary bit lines
4
. Each pair of bit lines
4
is associated with a respective read amplifier
5
and each bit line is connected to a supply line Vdd via a precharge transistor
6
. Row lines
3
are connected to a decoder
7
that receives an address A via a latch
8
rated by a read control clock signal CK. Precharge transistors
6
are controlled by a same precharge signal P. Read amplifiers
5
generate an output signal O.
To perform a reading, transistors
6
are first turned on for a duration sufficient to precharge complementary bit lines
4
to voltage Vdd, then transistors
6
are turned off and a row line
3
is activated by decoder
7
. Each pair of bit lines is then unbalanced according to the information stored in the cell of the selected row. When two read operations are performed in a row, the precharge that must come before the second reading deletes the data generated by the first reading. Thus, it is necessary to guarantee that the precharge for a current read operation is always performed after the end of the preceding read operation.
The function of a reference column
9
will be described hereafter.
FIG. 2
shows a memory of the type in
FIG. 1
, the precharge control signal P of which is obtained by inverting clock CK that rates the read operations.
FIG. 3
illustrates read operations on the circuit of FIG.
2
. At a time t
0
, address A provided to memory
1
changes. At a time t
1
that corresponds to the next rising edge of clock signal CK, address A is provided to decoder
7
by latch
8
. From time t
1
on, corresponding to the beginning of a read operation, output O of the memory starts changing and its state is undetermined (X). Output O is assumed to remain in an undetermined state for an unknown duration &Dgr; that corresponds to the response time of the slowest column of memory
1
.
At a time t
2
, at the end of duration &Dgr;, output O is assumed to be stable and it can be used. From a time t
3
on, corresponding to the next rising edge of control signal P, the precharge necessary to the next read operation starts. Output O is undetermined during the entire precharge interval, which here lasts until the next rising edge of clock signal CK. It should be noted that output O generated in a read cycle starting at time t
1
is stable and useable only between times t
2
and t
3
. Time t
2
depends on maximum read duration &Dgr;, which is a characteristic of memory
1
. Time t
3
depends on duration t
3
−t
1
, that is, on the duty cycle of signal CK.
FIG. 3
shows a signal CK with a duty cycle of one half, but it should be noted that if the latter decreases, duration t
3
−t
1
also decreases and may even become smaller than duration &Dgr;, in which case output O is deleted before being readable. Thus, in the case where precharge signal P is the complement of clock signal CK, a minimum value of the duty cycle of signal
CK has to be guaranteed, which is not always possible. It has thus been sought to generate a precharge control signal P independent from the duty cycle of clock signal CK.
FIG. 4
shows a memory
1
of the type in
FIG. 1
, the precharge control signal P of which is obtained by delaying clock signal CK with a delay line D.
FIG. 5
illustrates successive read operation on the circuit of
FIG. 4. t
D
designates the delay introduced by delay line D: precharge control signal P is activated at a time t
4
occurring at a duration t
D
after time t
1
. Output O generated in a read cycle that starts at a time t
1
is useable between above-mentioned time t
2
, which depends on duration &Dgr;, and time t
4
, which depends on duration t
D
of delay line D. The duty cycle of clock signal CK has no influence upon duration t
4
−t
2
. However, duration &Dgr; and delay t
D
vary according to the manufacturing method used, to temperature, as well as to other parameters. It is difficult to know these variations in advance, and a delay t
D
greater than necessary is chosen, to guarantee that duration t
4
−t
2
will always be sufficient to use output O.
Delay t
D
must however remain smaller than one period of signal CK, so that the precharge can occur during the read cycle. Thus, if delay t
D
is too long, the maximum operating frequency, and thus, the performances of memory
1
, have to be limited. It has thus been sought to provide a precharge control signal P with a delay that depends on the features of the memory. For this purpose, in
FIG. 1
, a reference column
9
, of same structure as a normal column and arranged at the distal end of precharge and row lines
3
, has been provided. With this configuration, reference column
9
is the latest one to provide a stable output O
1
during a read operation.
FIG. 6
shows a memory of this type, the precharge control signal P of which is generated based on output O
1
of the reference column by an edge detector
11
.
FIG. 7
illustrates read operations on the circuits of FIG.
6
. Signal O
1
is generated at a time t
5
, responsive to the edge of signal CK of time t
1
. &Dgr;
1
designates the duration elapsed between times t
1
and t
5
. For the previously discussed reasons, duration &Dgr;
1
is always greater than duration &Dgr;, whatever the features and operating conditions of memory
1
.
Edge detector
11
generates precharge control signal P responsive to signal O
1
at a time t
6
. &Dgr;
2
designates the duration between times t
5
and t
6
. It mainly depends on the propagation time of signal O
1
and on precharge control signal P. Duration &Dgr;
2
is relatively long, since the terminal that generates signal O
1
is far from the input terminals, especially from that on which precharge control signal P is provided. Durations &Dgr;
1
and &Dgr;
2
, which correspond to the memory width, increase with the size thereof. Now, the sum of durations &Dgr;
1
and &Dgr;
2
must remain smaller than one period of signal CK so that the precharge occurs in the read cycle. Thus, the larger a memory, the longer duration &Dgr;
1
+&Dgr;
2
, and the longer the period of signal CK has to be chosen, which limits the memory performances.
Thus, there is a need to overcome the disadvantages of the prior art as discussed above, and particularly to handle the problem of unknown delays during memory read cycles.
SUMMARY OF THE INVENTION
In view of these drawbacks, in accordance with an aspect the present invention it is intended to overcome the above-mentioned drawbacks and to provide, based on a clock signal, a precharge control signal that enables optimizing the memory reading rate.
A preferred embodiment of the present invention provides an integrated circuit generating an event responsive to an edge of an input signal and with an unknown delay, which includes means for providing an internal signal including several delay lines of different sizes that receive the edge of the input signal, a multiplexer, each input of which receives the output of one of the delay lines and the output of which gener

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