Memory with a variable impedance bit line load circuit

Details Memory with a variable impedance bit line load circuit Memory with a variable impedance bit line load circuit

1988-11-28

1991-12-24

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

For complementary information

36518909, 365203, G11C 11403

Patent

active

050758918

ABSTRACT:
A static random access memory (SRAM) includes a pair of p-channel metal-oxide-semiconductor (PMOS) transistors which serve as variable resistors for terminating bit lines and a control circuit for causing the PMOS transistors to have a low impedance level during read out and an intermediate impedance level during writing so that sudden d.c. current is suppressed and the voltage at the bit lines is prevented from being lowered. The variable resistor device can constitute a current mirror circuit along with a metal-insulator-semiconductor (MIS) transistor of the control circuit, so that it becomes possible to provide a stable control which is invulnerable to manufacturing tolerances.

REFERENCES:
patent: 4386419 (1983-05-01), Yamamoto
patent: 4636983 (1987-01-01), Young et al.
patent: 4730276 (1988-03-01), Waller
patent: 4791613 (1988-12-01), Hardee

Affiliated with

Also associated with

Rating

Memory with a variable impedance bit line load circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory with a variable impedance bit line load circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory with a variable impedance bit line load circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-49927