Memory using a single-node data, address and control bus

Details Memory using a single-node data, address and control bus Memory using a single-node data, address and control bus

2008-05-20

2008-05-20

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

C365S189040, C365S189050, C365S189110, C365S189180

Reexamination Certificate

active

11301670

ABSTRACT:
An integrated circuit digital device is coupled to a memory with a single-node data, address and control bus. The memory may be a non-volatile memory and/or volatile memory. The memory may be packaged in a low pin count integrated circuit package. The memory integrated circuit package may have a ground terminal, VSS; a power terminal, VDDor VCC; and a bidirectional serial input-output (I/O) terminal, SCIO. Memory block address set-up may be performed via software instructions through the SCIO terminal. In addition, hardwired memory block address selection terminals A0and A1may be used when more then three terminals are available on the memory integrated circuit package. The memory may have active pull-up and pull-down drivers coupled to the single-node data, address and control bus.

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International Search Report for PCT/US2006/047489 Mailed Jul. 5, 2007.

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