Memory with a selectable data width and reduced decoding logic

Static information storage and retrieval – Read/write circuit – Sipo/piso

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Details

365220, 39549702, G11C 700

Patent

active

057152055

ABSTRACT:
A method is described that writes a first and a second data of a first data width into a memory that stores data at a second data width greater than the first data width. The method includes the step of selecting via a select circuit a plurality of memory cells that correspond to the second data width from a memory array of the memory. The first data is then written into a first number of the memory cells corresponding to the first data width while writing invalid data into a second number of the memory cells also corresponding to the first data width during a first write operation. The second data is then written into the second number of the memory cells while again writing the first data into the first number of the memory cells during a second write operation. A memory that can operate with either the first data width or the second data width without changing its column select circuit is also described.

REFERENCES:
patent: 4286321 (1981-08-01), Baker
patent: 4975880 (1990-12-01), Knierim
patent: 5055661 (1991-10-01), Gochi
patent: 5262990 (1993-11-01), Mills
patent: 5373467 (1994-12-01), Wang
patent: 5396460 (1995-03-01), Harada
patent: 5504875 (1996-04-01), Mills
patent: 5546347 (1996-08-01), Ko et al.

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