Memory with auto refresh to designated banks

Details Memory with auto refresh to designated banks Memory with auto refresh to designated banks

2005-02-22

2005-02-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230030, C365S233100, C365S236000

Reexamination Certificate

active

06859407

ABSTRACT:
A memory comprising 2ndynamic random access memory (DRAM) banks, wherein n is an integer greater than or equal to 2, 2nrefresh row address counter circuits configured to generate 2nsets of refresh row address signals in response to 2nrefresh enable signals, a multiplexer circuit configured to provide the 2nsets of refresh row address signals to the 2nDRAM banks in response to the 2nrefresh enable signals, and a bank select circuit configured to provide 2nbank enable signals to the 2nDRAM banks in response to at least (n+1) external address signals and in response to the 2nrefresh enable signals is provided. The 2nbank enable signals cause at least two but less than all of the 2nDRAM banks to be refreshed using at least two of the 2nsets of refresh row address signals in response to the 2nrefresh enable signals.

REFERENCES:
patent: 5627791 (1997-05-01), Wright et al.
patent: RE36180 (1999-04-01), Lim
patent: 5959929 (1999-09-01), Cowles et al.
patent: 6192002 (2001-02-01), Merritt
patent: 6373769 (2002-04-01), Kiehl et al.
patent: 6529433 (2003-03-01), Choi
patent: 6587918 (2003-07-01), Christenson
patent: 6636450 (2003-10-01), Blodgett
patent: 6680869 (2004-01-01), Sonoda et al.

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