Timing fuse option for row repair
Topography correction for testing of redundant array elements
Tracking circuit for a memory device
Trap and patch system for virtual replacement of defective...
Twisted bit-line compensation for DRAM having redundancy
Two speed recirculating memory system using partially good compo
Universal modular memory
Use of redundant circuits to improve the reliability of an integ
User programmable redundant memory
Using redundant memory for extra features
Using redundant memory for extra features
Using redundant memory for extra features
Variable column redundancy region boundaries in SRAM
Variable size redundancy replacement architecture to make a memo
Word group redundancy scheme
Word line redundancy nonvolatile semiconductor memory
Wordline and bitline redundancy with no performance penalty
Write driving circuit
Zero power CMOS redundancy circuit
Zero standby power, radiation hardened, memory redundancy circui