Zero power CMOS redundancy circuit

Details Zero power CMOS redundancy circuit Zero power CMOS redundancy circuit

1984-01-06

1986-09-23

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

365227, 307441, 307219, 371 10, G11C 700, H01J 1982, H03K 1782, G06F 1100

Patent

active

046139591

ABSTRACT:
A redundancy circuit that consumes no power before or after activation switches a pair of output nodes from a first set of complementary logic levels to an inverted set when it is activated by blowing a pair of fuses.

REFERENCES:
patent: 4346459 (1982-08-01), Sud et al.
Sud et al., "Designing Static Rams for Yield as Well as Speed", Electronics, Jul. 28, 1981, pp. 121-126.

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