Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1997-03-31
1998-11-03
Yoo, Do Hyun
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 36523003, 36523006, G11C 700
Patent
active
058319140
ABSTRACT:
A variable size redundancy replacement (VSRR) arrangement for making a memory fault-tolerant. A redundancy array supporting the memory includes a plurality of variable size redundancy units, each of which encompasses a plurality of redundancy elements. The redundancy units, used for repairing faults in the memory, are independently controlled. All the redundancy elements within a repair unit are preferably replaced simultaneously. The redundancy elements in the redundancy unit are controlled by decoding address lines. The variable size that characterizes this configuration makes it possible to choose the most effective redundancy unit, and in particular, the one most closely fitting the size of the cluster of failures to be replaced. This configuration significantly reduces the overhead created by added redundancy elements and control circuitry, while improving the access speed and reducing power consumption. Finally, a fault-tolerant block redundancy controlled by a priority decoder makes it possible to use VSRR units for repairing faults in the block redundancy prior to its use for replacing a defective block within the memory.
REFERENCES:
patent: 5295101 (1994-03-01), Stephens, Jr. et al.
patent: 5430679 (1995-07-01), Hiltebeitel et al.
patent: 5459690 (1995-10-01), Rieger et al.
patent: 5461587 (1995-10-01), Oh
patent: 5475648 (1995-12-01), Fujiwara
patent: 5491664 (1996-02-01), Phelan
patent: 5691945 (1997-11-01), Liou et al.
patent: 5691946 (1997-11-01), DeBrosse et al.
patent: 5703817 (1997-12-01), Shiratake et al.
patent: 5724295 (1998-03-01), Beiley et al.
H. L. Kalter, et al, "A 50-ns 16-Mb DRAM with a 10-ns Data Rate and O-Chip ECC" IEEE Journal of Solid-State Circuits, V. 25, Oct. 1990, pp. 1118-1128.
T. Kirihata, et al, "A 14-ns 4-Mb CMOS DRAM with 300-mW Active Power" IEEE Journal of Solid-State Circuits, V. 27, Sep. 1992, pp. 1222-1228.
T. Sugibayashi, et al, "A 30ns 256Mb DTAM with Multi-Divided Array Structure" IEEE Journal of Solid-State Circuits, V. 28, Nov. 1993, pp. 1092-1098.
T. Kirihata, et al, "Fault-Tolerant Designs for 256 Mb DRAM" IEEE Journal of Solid-State Circuits, V. 31, Apr. 1996, pp. 558-566.
International Business Machines - Corporation
Schnurmann H. Daniel
Yoo Do Hyun
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