Wordline and bitline redundancy with no performance penalty

Details Wordline and bitline redundancy with no performance penalty Wordline and bitline redundancy with no performance penalty

1997-01-17

1998-08-11

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36518902, G11C 700

Patent

active

057936838

ABSTRACT:
Wordline and bitline redundancy is provided in large memory arrays but without the performance penalty normally associated with the redundancy calculation. All redundant elements are placed in a redundant array. Defective wordlines are mapped into blocks of cells of the redundant array and defective bitlines are mapped into blocks of cells of the redundant array. The redundant array is accessed based on the result of the redundancy calculation. This allows the redundant array to be architected with very few cells per bitline and therefore it can be accessed much more quickly than the normal memory array.

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"Improved Logic Redundancy Architecture With Performance Enhancements", IBM Technical Disclosure Bulletin, vol. 36, No. 1, Jan. 1993, pp. 197-199.

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