Two speed recirculating memory system using partially good compo

Details Two speed recirculating memory system using partially good compo Two speed recirculating memory system using partially good compo

1980-09-15

1982-12-21

Stellar, George G.

Static information storage and retrieval

Read/write circuit

Bad bit

365 73, 371 10, 371 11, G11C 700, G11C 2100

Patent

active

043653189

ABSTRACT:
A CCD recirculating memory system is disclosed in which "partially good" CCD memory chips and "all good" memory chips are mounted on memory cards. The defective portions of the partially good chips are in the same chip octants on the same card. The cards are addressed by address permutation means which causes the defective portions to appear to have the same predetermined address to the operating system.
The addressed CCD row on the partially good chips are clocked at a fast rate while the unaddressed rows are clocked at a slow rate. All of the rows of the "all good" chips are clocked at a fast rate when a defective portion of the partially good chips is being addressed and are otherwise clocked at a slow rate.
A select signal is generated whenever the predetermined address is invoked and causes the substitution of an all good chip for the addressed partially good chip. The select signal also selectively prevents another memory access from occurring until resynchronization is achieved between the last accessed chip and the unaccessed chips. The arrangement minimizes waiting time between successive memory accesses in a two speed partially good recirculating array without the need to map and store the defective locations on the partially good chips employed.

REFERENCES:
patent: 3654610 (1972-04-01), Sander et al.
patent: 3755791 (1973-08-01), Arzubi
patent: 3765001 (1973-10-01), Beausoleil
patent: 3781826 (1973-12-01), Beausoleil
patent: 3845476 (1974-10-01), Boehm
patent: 3976179 (1976-10-01), Elmer et al.
patent: 4066880 (1978-01-01), Salley
patent: 4089063 (1978-05-01), Takezono

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