Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1994-05-27
1995-06-20
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
365185, 365218, 365900, G11C 700
Patent
active
054266084
ABSTRACT:
An object of the present invention is to realize a flash memory in which word redundancy can be implemented. In a nonvolatile semiconductor memory of the present invention in which word redundancy is implemented to replace a faulty memory cell with a redundancy nonvolatile memory cell in units of a word line, source lines are a plurality of lines arranged in a one-to-one correspondence with and in parallel with word lines. The source lines are connected to a first common source line via first switching means that are selectively allowed to conduct owing to voltage applied to word lines for reading or writing. The source lines are connected to a second common source line via second switching means that conduct for erasing.
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Patent Abstracts of Japan, vol. 17, No. 626 (P-1647) & JP-A-05 198 190 Aug. 6, 1993.
Dinh Son
Fujitsu Limited
Popek Joseph A.
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