Word group redundancy scheme

Details Word group redundancy scheme Word group redundancy scheme

1982-02-26

1984-07-24

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

G11C 1140

Patent

active

044620918

ABSTRACT:
A word redundancy scheme for a high speed RAM where the bit output stage uses on-chip logic. An extra emitter on each of the decoders is utilized including redundant word group decoders. A compare circuit has an output to each of the extra emitters and when the address of a bad bit arrives at the compare circuit it de-selects each of the non-redundant decoders at that address and selects the redundant decoders via the extra emitters. Hence, the redundant decoders replace the decoders of the bad bit position.

REFERENCES:
patent: 4346459 (1982-08-01), Sud et al.
Chan et al., "Array Word Redundancy Scheme", IBM Technical Disclosure Bulletin, vol. 25, No. 3A, Aug. 1982, pp. 989-992.
Beausoleil, "Utilization of Defective Memory Chips by Substituting Redundant Words for Defective Words", IBM Tech. Disc. Bull., vol. 15, No. 6, Nov. 1972, pp. 1864-1865.

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