Topography correction for testing of redundant array elements

Details Topography correction for testing of redundant array elements Topography correction for testing of redundant array elements

2002-09-24

2004-06-22

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

06754113

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor device design, and more particularly, to a device and method for testing memory arrays having redundant elements with different data topologies.
2. Description of the Related Art
Referring to
FIG. 1
, a conventional semiconductor memory device
100
includes a plurality of wordlines (WL) and a plurality of bitlines (BL) arranged to intersect the wordlines to form a memory cell array
102
. Individual memory cells
104
are arranged at respective intersections of the wordlines and bitlines. A row decoder
106
, a column decoder
108
, and an input/output circuit
110
are provided in relation to the memory cell array
102
. The row decoder
106
decodes a row address applied through an address input line
112
to select one of the wordlines, and applies a voltage to the selected wordline. The input/output circuit
110
includes a plurality of switching circuits each corresponding to a bitline pair (a true bitline BL and a complement bitline {overscore (BL)}), and one or a plurality of sense amplifiers disposed between an input/output line
114
and the switching circuits. The column decoder
108
decodes a column address applied through the address input line
112
to select one of the switching circuits. The input/output line
114
is connected to a data input/output pad (not shown) through an output driver circuit (not shown). Therefore, one memory cell
104
is selected by the row decoder
106
and the column decoder
108
.
Arrays on memory devices usually require the usage of redundant array elements to fix any processing manufacturing defects to increase yield, i.e., redundant memory elements will replace defective memory elements to enable repairablity of the array. These redundant memory elements may include redundant rows/redundant wordlines RWL or spare column select lines CSL. For example, a column replacement is usually accomplished by four pairs of bitlines that are accessed by the same column select line CSL. These redundant elements increase the layout complexity of the semiconductor memory device. Furthermore, array architecture complexity increases with the usage of Bit Line (BL) twisting schemes (see
FIG. 1
“TWIST”) and layout mirroring/packaging schemes.
These increases in complexity will either cause data topologies between redundant elements and the replaced defective elements to be different sometimes or it will limit the possible replacement candidates that a defective element could be replaced with. The data topology determines how a memory cell will store a particular value. For example, a memory cell can represent a logical “1” by storing either a positive or use charge (similar to a logical “0”). What determines whether a logical “1” is stored as a positive or “0” charge, is by how the sense amplifier is connected to the memory cell. If the memory cell is on a true bitline BL, a positive charge will be stored and, if the memory cell is on a complement bitline {overscore (BL)}, a “0” charge will be stored.
Having a different data topology after being repaired will not affect the normal functionality of the memory device. However, it may cause reduced test coverage or hard to analyze results during post-fuse testing. For example, if a complement redundant wordline {overscore (RWL)} is used to replace a defective true wordline WL, when testing for retention fail of solid “1” data, the complement redundant wordline {overscore (RWL)} and redundant memory cell
116
will have physical “0” stored and it will not be truly tested for retention.
SUMMARY OF THE INVENTION
Accordingly, it is an aspect of the present invention to provide a data topography correction circuit for a semiconductor memory device including a redundant hit circuit for determining if a redundant element has been used to replace a defective element of the semiconductor memory device; and a redundant topology correction scrambler circuit for converting data from a data topology of the defective element to a data topology of the redundant element. The redundant hit circuit is adapted to compare a memory element address to repair fuse information to determine if addressed memory element has been replaced with a redundant element.
The data topography correction circuit further includes a first multiplexer for multiplexing corrected data with raw data to a memory array of the semiconductor memory device upon a write operation; and a second multiplexer for multiplexing corrected data with raw data to an off-chip driver from the semiconductor memory device upon a read operation.
According to another aspect of the present invention, a semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including a plurality of memory elements and a plurality of redundant memory elements; and a data topography correction circuit including a redundant hit circuit for determining if a redundant memory element has been used to replace a defective memory element of the semiconductor memory device; and a redundant topology correction scrambler circuit for converting data from a data topology of the defective memory element to a data topology of the redundant memory element. The semiconductor memory device further includes a first multiplexer for multiplexing corrected data with raw data to a memory array of the semiconductor memory device upon a write operation; and a second multiplexer for multiplexing corrected data with raw data to an off-chip driver from the semiconductor memory device upon a read operation.
According to a further aspect of the present invention, a method for testing a semiconductor memory device includes the steps of applying a test mode signal to place the semiconductor memory device in a test mode; providing an address of a memory array element of the semiconductor memory device to be tested; determining if the memory array element has been replaced with a redundant element; and if the memory array element has been replaced, correcting test data to a data topology of the redundant element.
According of another aspect of the present invention, the method further includes the step of comparing the address of the memory array to repair fuse information to determine if the memory array element has been replaced with a redundant element.
Furthermore, the method can be performed during a write or read operation.


REFERENCES:
patent: 6097644 (2000-08-01), Shirley
patent: 2001/0046166 (2001-11-01), Fischer et al.

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