Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-09-27
2002-07-16
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C714S710000, C714S711000
Reexamination Certificate
active
06421283
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to volatile memory devices such as Random Access Memories (RAM), and more particularly, to systems for identifying defective RAM memory cells and virtually replacing the defective cells with operable memory cells.
2. Related Art
Very large scale integrated circuit devices (VLSI), such as application specific integrated circuits (ASIC's), are continually increasing in size, and the volatile memory (RAM) in such devices is also increasing. Larger devices generally have a lower yield due to the large number of components and connections that are on each circuit chip. The lower yield can increase cost significantly. If even one memory cell (bit) of RAM is defective, an entire device can potentially be rejected and lost.
Several techniques have been developed to address this problem. For example, redundancy has been added to improve the ability of the system to operate with a few bit errors. In such devices, extra memory cells called redundant cells are made when the device is fabricated. The redundant cells are used to replace defective cells by changing the circuit connections after the device is tested. This is another step in the fabrication process. However, this solution requires extra memory cells, that adds to cost. The resources required to rewire the device also increase cost.
Another known solution is to increase the RAM word width from perhaps 8 bits to 9-10 bits, and add parity bit(s) detection to identify defects through a parity check. Then, a software RAM table can be adjusted to avoid the bad cells. However, this requires an extra memory for the parity bits, which is undesirable due to cost.
Defective software code replacement in read only memory (ROM) has been accomplished using a “trap and patch” approach to code replacement. In the trap and patch method, logic is used to replace one or more lines of code stored in ROM with lines of code stored in RAM, in a way that is transparent to the central processing unit (CPU).
An example of trap and patch code replacement in ROM is seen in FIG.
1
. An application specific integrated circuit (ASIC) or other integrated circuit
600
may include a CPU
302
, ROM
304
, RAM
106
and trap and patch (T&P) logic
308
. As the CPU
302
runs, it sends address requests on an address line
310
to the ROM
304
, and data is returned on a data line
112
. The ROM
304
might contain a program having steps
1
-
10
, as seen in FIG.
2
.
If some of the code stored in the ROM is defective or out-dated, trap and patch code (developed in the factory to replace the unwanted code) is stored in a nonvolatile RAM (NVRAM)
316
. When the unit is powered up or reset (PoR), the NV RAM
316
loads the trap and patch software in the RAM
106
, and loads trap addresses
118
in the T&P logic
308
. The T&P logic
308
cuts off the data output of the ROM
304
in a gate
320
when a trap address is recognized, and sends the replacement code stored in the RAM
106
to the CPU over a line
322
.
This process might only be needed at power on/reset, since the CPU can then normally run from RAM if instructed to “jump” execution to the RAM address. Code execution redirection can be accomplished in other ways, such as through a special CPU interrupt that instantaneously changes code source.
For example, if steps
4
,
5
and
6
in the program
114
are defective, the factory programs the NV RAM
316
so that the trap and patch logic
308
detects
3
on the address line
310
, closes the gate
320
, and replaces the bad code with steps
27
,
28
and
29
in patch code stored in the RAM
106
(FIG.
2
). In this manner, the defective code for steps
4
,
5
and
6
is replaced with steps
27
,
28
and
29
, after which gate
320
opens and the routine is returned to step
7
in the program
114
. A defect in step
10
can be replaced with perhaps lines
7
,
8
and
9
of RAM code in a similar manner. In this manner, the defective code is replaced in a manner that is transparent to the CPU.
While the trap and patch method has been successfully used to replace code stored in ROM, the concept has not been applied to RAM. Thus, there is still a need for a system capable of replacing defective RAM memory cells, to increase manufacturing yields and decrease cost. Conventional ROM trap and patch systems rely on the factory to identify defective code, so if even one ROM memory cell is lost in the field, the system cannot recover and usually fails. Thus, there is also a need for trap and patch methods which identify and virtually replace defective memory cells on the fly.
SUMMARY
An integrated circuit device may include a central processing unit (CPU), volatile RAM and read only memory (ROM). Trap and patch (T&P) logic circuits and a plurality of trap and patch registers may also be provided. The volatile RAM, that can include one or more physical memories, may have a number of memory cells that are allocated for operation of the device, and a number of other memory cells that are allocated for virtual defective memory cell replacement.
When the device is manufactured, the entire RAM is tested by a program on the device or on a tester, to identify bad memory locations. If the total number of RAM errors in the memory cells for device operation is greater than the number of trap and patch logic circuits and registers, or if RAM used for diagnostic program execution is bad, the device is rejected. If not, the device can be used.
When power is turned on or the system is reset (PoR), the CPU executes a diagnostic program stored in ROM that identifies defective RAM memory locations among the memory cells used for operating purposes. The CPU then loads the T&P logic and trap registers with the defective addresses and the replacement or patch RAM locations (addresses). When the CPU reads or writes to the bad RAM locations, the T&P logic cuts off access to the RAM and inserts the patch addresses of the replacement RAM memory locations for the reading and writing operations. This virtual memory cell replacement is transparent to the CPU. Since the diagnostic program is run on every PoR, cells which become defective in the field can be identified and replaced, averting a system failure.
In another embodiment of the invention, the defective memory locations and trap addresses are stored in nonvolatile random access memory (NV RAM) at the factory or by the embedded diagnostic program. Once stored in NV RAM, the trap and patch address information can be loaded more quickly.
Other systems, methods, and features of the invention will be apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods and features be included within this description, be within the scope of the invention, and be protected by the accompanying claims.
REFERENCES:
patent: 5758056 (1998-05-01), Barr
patent: 5986952 (1999-11-01), McConnell et al.
patent: 6141768 (2000-10-01), Lin et al.
patent: 6198663 (2001-03-01), Takizawa
Cho Dong
Walley John S.
Conexant Systems Inc.
Greer Burns & Crain Ltd.
Nelms David
Yoha Connie C.
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