Direct access to random redundant logic gates by using multiple
Disabling a decoder for a defective element in an integrated cir
Disk array system and method for storing data
Distributed block redundancy for memory devices
Double word line type dynamic RAM having redundant sub-array of
Double-row address decoding and selection circuitry for an elect
DRAM array with gridded sense amplifier power source for enhance
Dram array with gridded sense amplifier power source for...
DRAM repair apparatus and method
Drive failure recovery via capacity reconfiguration
Dual comparator circuit and method for selecting between normal
Dual port semiconductor memory device
Dual-port memory device
Dual-ported CAMs for a simultaneous operation flash memory
Dummy memory cells for high accuracy self-timing circuits in...
Dynamic address remapping decoder
Dynamic address remapping decoder
Dynamic column redundancy driving circuit for synchronous semico
Dynamic memory circuit including spare cells
Dynamic memory having two modes of operation