Direct access to random redundant logic gates by using multiple

Details Direct access to random redundant logic gates by using multiple Direct access to random redundant logic gates by using multiple

1998-09-04

2000-02-01

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

365201, G11C 700

Patent

active

060210745

ABSTRACT:
The present invention provides a method for accessing a plurality of gates in a random logic structure. The method includes the steps of providing a first address for a first line coupled to a gate, providing a second address for a second line coupled to the gate, providing at least one additional address for at least one additional line coupled to the gate, and accessing the gate at the intersection of the first, second, and additional addresses. A method for accessing random logic gates which allows for the testing of more logic gates than conventional methods and which is also faster than conventional methods has been disclosed. The method of the present invention provides a three or more dimensional (segmented) address for each gate which allows for the status of more gates to be specifically ascertained. This allows for more ease in testing, saving valuable time. The method of the present invention also has the added advantage of allowing repair of defective gates with redundant gates.

REFERENCES:
patent: 5701270 (1997-12-01), Rao
patent: 5719879 (1998-02-01), Gillis et al.

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