Dynamic address remapping decoder

Details Dynamic address remapping decoder Dynamic address remapping decoder

1997-06-09

1999-07-06

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, 371 213, G11C 700

Patent

active

059205121

ABSTRACT:
A memory system comprising a memory controller, first and second memory arrays, and a decoder is provided. The memory arrays comprise at least one section having all good memory locations, and at least one section having at least one faulty memory location. The decoder is responsive to the memory controller for selectively enabling data transfer between the controller and the sections of the first and second memory arrays having all good memory locations.

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