Double word line type dynamic RAM having redundant sub-array of

Details Double word line type dynamic RAM having redundant sub-array of Double word line type dynamic RAM having redundant sub-array of

1993-09-30

1995-05-09

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365 63, G11C 2900

Patent

active

054146607

ABSTRACT:
In a double word line type dynamic RAM, redundant memory cells to be substituted for defective cells are concentrated so as to form only one redundant sub-array in a row direction and in a column direction. The size of the redundant sub-array is made smaller than that of regular sub-arrays each composed of only regular cells. Although a minimum unit of cells to be replaced together becomes large in the double word line type dynamic RAM, the increase of the redundant memory cells can be effectively suppressed.

REFERENCES:
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"A Boosted Dual Word-line Decoding Scheme for 256Mb DRAMs", Noda, et al., IEEE, Feb., 1992, Symposium on VLSI Circuits Digest of Technical Papers.
"A Flexible Redundancy Technique for High-Density DRAM's", Horiguchi, et al., IEEE, Jan., 1991, Journal of Solid State Circuits.

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