Dynamic column redundancy driving circuit for synchronous semico

Details Dynamic column redundancy driving circuit for synchronous semico Dynamic column redundancy driving circuit for synchronous semico

1997-10-17

1999-09-28

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, G11C 700

Patent

active

059599049

ABSTRACT:
A dynamic column redundancy driving circuit for a synchronous semiconductor memory device is provided. The circuit includes a first node, a precharging portion, an address determining portion, a clock delay portion, and a driving portion. The precharging portion precharges the first node in the first phase of the clock. The address determining portion is connected to the first node and includes a plurality of fuses selectively disconnected according to a defect address and changes a logic level of the first node in the second phase of the clock according to whether an address matches the defect address. The clock delay portion delays the clock. The driving portion receives the output of the address determining portion and the output of the clock delay portion and produces a redundancy wordline driving signal.

REFERENCES:
patent: 5677882 (1997-10-01), Isa et al.
patent: 5703824 (1997-12-01), Isa

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