Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-02-11
2001-03-20
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189050, C365S196000, C365S225700, C365S226000
Reexamination Certificate
active
06205066
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor memory devices and, in particular, to dynamic random access memory (DRAM) devices with a gridded sense amplifier power source for enhanced column repair.
2. Description of the Related Art
Integrated circuits contain a number of active semiconductor devices formed on a chip (“die”) of silicon and these devices are interconnected to package leads to form a complete circuit.
An essential semiconductor device is the semiconductor memory, such as random access memories (RAM), which generally are constructed with an array of individual memory cells on a cell plate. A RAM allows the user to execute both read and write operations on its memory cells. Dynamic random access memory (DRAM) is a specific category of RAM containing an array of individual memory cells, where each includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor.
FIG. 1
shows an exemplary DRAM cell array
5
. The array
5
includes word lines
18
and bit lines
10
which are commonly arranged in rows and columns, respectively. Each individual memory cell
20
is capable of storing one data bit and is composed of a voltage source line
24
, capacitor
26
, and transistor
28
and is accessed by activating an associated word and bit line. The transistor
28
may be either a pMOS or nMOS transistor and the choice of either will determine the voltage carried by the word line
18
. The charge held in capacitor
26
is representative of a data bit of either a logical “1” or logical “0,” symbolizing a high or low voltage, respectively. The data may be accessed during a read operation or stored during a write operation.
Data is read from the memory cell
20
by firing a word line driver
32
to activate a word line
18
, which couples all of the memory cells corresponding to that word line
18
or row to respective bit lines
10
which define the columns of the array
5
. One or more bit lines are also activated. When a particular word line
18
and bit lines
10
are activated, a sense amplifier
80
connected to a bit line column (defined by a pair of bit lines
10
) detects and amplifies the data bit transferred from the capacitor
26
to a bit line
10
by measuring the potential difference between the activated bit line
10
and a reference line which may be an inactive bit line
10
. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc. and incorporated by reference herein.
For a read/write operation to be successful, there must be no defects along a row or column. A common defect is a short
30
between a bit line
10
and a word line
18
. The presence of a short
30
prohibits the charge held in the capacitor
26
from being reliably sensed. This is an increasingly common problem in the construction of DRAM devices because of the rapid advancement in increasing the density of cell arrays. This rise in the number of cells per chip, or stated otherwise, the decrease in cell size and other geometries, increases the probability that a defect will be present. Another common defect is the existence of a short
40
between a bit line
10
and the cell plate, a sheet in the array that acts as one of the plates of the storage node capacitors
26
. Various methods have been devised to test memory cell arrays to determine which memory cells are defective.
Today, instead of destroying a DRAM containing a number of defects, methods have been devised to repair the defective portions of the memory array and allow the repaired DRAM to be used. One of the most common methods of repairing defective arrays is by the creation and use of rows and columns of redundant memory cells. The majority of DRAMs contain some type of mechanism for the replacement of defective cells with redundant cells, a process known as “repairing out.” Typically, this process uses a combination of fuses and addressing circuitry to remove the defective cells from use and redirect addressing signals to a redundant row or column which, in turn, accesses a redundant cell. Frequently, a grouping of cells along a word and/or bit line are substituted as a group due to the adverse effect that one defective cell has on the remaining cells along their common word line.
While this type of repair allows the DRAM to be operational, it does not remove the defective memory cells from the chip surface, the process merely redirects signals around the defective cells. The repaired-out cells may still adversely effect the performance of a DRAM in terms of both speed and reliability and in the sensing robustness of the remaining cells.
Shown in
FIG. 1
is a bit line
10
to cell plate short
40
. The existence of cell plate short
40
may lead to corruption of the sensing of other bit lines
10
on the die even after it has been detected and repaired out. When a sense amp
80
for a bit line pair is still operational and commences firing it will pull one bit line
10
to Vcc and the other to Vss when a row in that array is accessed. The cell plate is normally being driven to Vcc/2 by the bias voltage generator during the activation of sense amp
80
. Because of the short, the cell plate is pulled to the voltage held by the bit line
10
, either Vcc or Vss. In the case wherein the cell plate has been driven to Vss, a charge written back into the open word line
18
may also be driven to Vss. When the sense amps are then turned off, the cell plate returns to Vcc/
2
, and the charge storage node
26
couples to Vcc/
2
because of the short through the bit line
10
. On the next cycle when the memory cell
28
is read, the voltage of the cell
28
is at Vcc/
2
, which is indistinguishable as either a logical “1” or “∅”.
The existence of a short
30
between word line
18
and bit line
10
, as shown in
FIG. 1
, may lead to sensing problems in the array even if short
30
has been repaired out. This can be demonstrated by the effect this has on the typical circuitry of a DRAM column
100
, shown in FIG.
2
.
FIG. 2
shows a schematic view of a column line pair
101
framed by bit lines
102
and
104
. Equilibration gating lines (EQ)
108
,
132
and nMOS transistors
106
,
134
effectively equalize the charges held by bit lines
102
and
104
after a read/write operation is completed and when that array is not active. Frequently, the column circuitry
100
is combined with a bias voltage generator (not shown) to maintain the voltages across the bit lines
102
,
104
at a voltage, commonly Vcc/2 (also known as DVC2), where Vcc is the voltage supplied to the chip containing the DRAM. The bias voltage generator will also maintain the cell plate charge at Vcc/2 as well. Other components of column circuitry
100
include isolation gating lines (ISO)
110
,
126
and nMOS transistors
112
,
114
and
128
,
130
forming isolation devices to effectively remove certain sensors during addressing. The actual sensing and amplification is performed by the n-sense amplifier
80
controlled by the n-sense amplifier latching signal (NLAT)
116
, and the p-sense amplifier
120
controlled by the p-sense amplifier latching signal (PLAT)
122
, which work in conjunction to effectively read a data bit which was stored in a memory cell
20
before being transferred to bit line
102
.
Since a short
30
between a word line and bit line can not be physically removed from the cell array, the short is still in existence and can result in unacceptably high standby current even though a redundant row or column of cells is substituted to remove faulty cells. This is because the equilibrated bit lines
102
,
104
are connected to a bias voltage generator biasing the bit lines
102
,
104
to Vcc/2 and a word line (not shown) is biased at a voltage Vss (preferably ground). Therefore, the word line will drive both the bit lines and the bias voltage generator toward ground. If the bias voltage generator cannot overcome this drain, its current production m
Dickstein , Shapiro, Morin & Oshinsky, LLP
Elms Richard
Micro)n Technology, Inc.
Nguyen Vanthu
LandOfFree
Dram array with gridded sense amplifier power source for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dram array with gridded sense amplifier power source for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dram array with gridded sense amplifier power source for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2521544