Double-row address decoding and selection circuitry for an elect

Details Double-row address decoding and selection circuitry for an elect Double-row address decoding and selection circuitry for an elect

1994-12-15

1996-12-03

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 36518509, G11C 700

Patent

active

055815090

ABSTRACT:
A double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy comprises a plurality of identical circuit blocks supplied with address signals and each one generating a respective selection signal which is activated by a particular logic configuration of said address signals for the selection of a particular row of the matrix; each one of said circuit blocks also generates a carry-out signal which is supplied to a carry-in input of a following circuit block and is activated when the respective selection signal is activated; a first circuit block of said plurality of circuit blocks has the respective carry-in input connected to a reference voltage; each of said circuit blocks is also supplied with a control signal, which is activated by a control circuitry of the memory device when, during a preprogramming operation preceding an electrical erasure of the memory device, a defective row is addressed, to enable the activation of the respective selection signal if the carry-out signal supplying the respective carry-in input is activated, so that two adjacent rows can be simultaneously selected.

REFERENCES:
patent: 4584674 (1986-04-01), Watanabe
patent: 4852066 (1989-07-01), Kai

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