Distributed block redundancy for memory devices

Details Distributed block redundancy for memory devices Distributed block redundancy for memory devices

1998-12-10

2000-01-25

Nelms, David

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, G11C 700

Patent

active

060184833

ABSTRACT:
A memory bank, in accordance with the present invention includes a plurality of memory sub-units, each memory sub-unit being divided by sense amplifier banks wherein adjacent memory sub-units share the sense amplifier bank therebetween. Redundancy regions are also included which are disposed in the memory sub-units and sharing circuitry therewith. The redundancy regions are located at a first end portion and a second end portion of the memory bank, the first and second end portions being disposed at opposing ends of the memory bank. A central sense amplifier bank is disposed between a first half and a second half of the memory bank wherein failed devices in the first half of the memory bank are replaced by a device in the redundancy region at the first end portion and failed devices in the second half of the memory bank are replaced by a device in the redundancy region at the second end portion such that sense amplifier contention is prevented for the central sense amplifier bank. Also, a method for replacing failed devices is disclosed.

REFERENCES:
patent: 5355339 (1994-10-01), Oh et al.
patent: 5475648 (1995-12-01), Fujiwara
patent: 5491664 (1996-02-01), Phelan
patent: 5691946 (1997-11-01), DeBrosse et al.
patent: 5831913 (1998-11-01), Kirihata
patent: 5831914 (1998-11-01), Kirihata
patent: 5881003 (1999-03-01), Kirihata et al.

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