Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1997-09-26
1998-11-24
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Bad bit
36518509, 36518907, G11C 700
Patent
active
058417125
ABSTRACT:
A redundancy circuit and method allows replacement of failed memory cells in a semiconductor memory array. Redundancy true and redundancy not comparator circuits are provided in dynamic logic to selectively enable and disable respective redundant row predecode and normal row predecode circuits. In one embodiment, redundancy circuits are row redundancy circuits. As compared with single static row redundancy comparator circuits which are limited by setup time constraints and which degrade access time irrespective of redundant row utilization, a dual dynamic comparator design reduces access time penalties when redundancy is enabled and eliminates access time penalties when redundancy is not required in a particular semiconductor memory array.
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Wendell Dennis L.
Wong Benjamin S.
Advanced Micro Devices , Inc.
Nelms David C.
Nguyen Hien
O'Brien David W.
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