Applying different body bias to different substrate portions...
Applying negative gate voltage to wordlines adjacent to...
Approach to provide high external voltage for flash memory erase
Architecture and method for NAND flash memory
Architecture and method for performing page write/verify in a fl
Architecture for a flash erase EEPROM memory
Architecture for a flash-EEPROM simultaneously readable in...
Architecture for assisted-charge memory array
Architecture for virtual ground memory arrays
Architecture of a non-volatile electrically erasable and...
Architecture of a nvDRAM array and its sense regime
Architecture to suppress bit-line leakage
Area efficient implementation of small blocks in an SRAM array
Arrangement for storing a count
Array and pitch of non-volatile memory cells
Array architecture and operating methods for digital...
Array architecture and operating methods for digital...
Array architecture and operating methods for digital...
Array architecture and operation methods for a nonvolatile...
Array architecture nonvolatile memory and its operation methods