Architecture for assisted-charge memory array

Details Architecture for assisted-charge memory array Architecture for assisted-charge memory array

2007-04-17

2007-04-17

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S063000

Reexamination Certificate

active

11326855

ABSTRACT:
An Assisted Charge (AC) Memory cell includes a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The gate electrode can include a trapping layer. The trapping layer can be treated as electrically split into two sides. One side can be referred to as the “AC-side” and can be fixed at a high voltage by trapping electrons within the layer. The electrons are referred to as assisted charges. The other side of can be used to store data and is referred to as the “data-side.” The abrupt electric field between AC-side and the data-side can enhance programming efficiency.

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C.C. Yeh, et al., “Phines: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory”, 2002 IEEE, IEDM 931-934.
Jan Van Houdt, et al., “Analysis of the Enhanced Hot-Electron Injection in Split-Gate Transistors Useful for EEPROM Applications”, IEEE Transactions on Electron Devices, vol. 39, No. 5, May 1992.

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