Architecture and method for performing page write/verify in a fl

Static information storage and retrieval – Floating gate – Particular biasing

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

365154, 36518508, 36523005, G11C 1606

Patent

active

06122197&

ABSTRACT:
A semiconductor non-volatile memory device is disclosed which is based on the use of Fowler-Nordheim electron tunneling to charge and discharge the isolated gates of the storage cells. The disclosed memory device includes circuitry capable of verifying the threshold level of written storage cells and rewriting only those cells whose threshold is outside a desired threshold range. The disclosed circuit has the further advantage of being able to load data words and verify cell contents simultaneously by utilizing both ends of the bit lines.

REFERENCES:
patent: 5590073 (1996-12-01), Arakawa et al.
patent: 5812451 (1998-09-01), Iwata
patent: 5835414 (1998-11-01), Hung et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Architecture and method for performing page write/verify in a fl does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Architecture and method for performing page write/verify in a fl, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture and method for performing page write/verify in a fl will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1079941

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.